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19-3271; Rev 0; 5/04
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs
General Description
The MAX1224/MAX1225 low-power, high-speed, serialoutput, 12-bit, analog-to-digital converters (ADCs) operate at up to 1.5Msps. These devices feature true-differential inputs, offering better noise immunity, distortion improvements, and a wider dynamic range over singleended inputs. A standard SPITM/QSPITM/MICROWIRETM interface provides the clock necessary for conversion. These devices easily interface with standard digital signal processor (DSP) synchronous serial interfaces. The MAX1224/MAX1225 operate from a single +2.7V to +3.6V supply voltage and require an external reference. The MAX1224 has a unipolar analog input, while the MAX1225 has a bipolar analog input. These devices feature a partial power-down mode and a full power-down mode for use between conversions, which lower the supply current to 1mA (typ) and 1A (max), respectively. Also featured is a separate power-supply input (VL), which allows direct interfacing to +1.8V to VDD digital logic. The fast conversion speed, low-power dissipation, good AC performance, and DC accuracy (1.5 LSB INL) make the MAX1224/MAX1225 ideal for industrial process control, motor control, and base-station applications. The MAX1224/MAX1225 come in a 12-pin TQFN package, and are available in the commercial (0C to +70C) and extended (-40C to +85C) temperature ranges. 1.5Msps Sampling Rate Only 18mW (typ) Power Dissipation Only 1A (max) Shutdown Current High-Speed, SPI-Compatible, 3-Wire Serial Interface 69dB S/(N + D) at 525kHz Input Frequency Internal True-Differential Track/Hold (T/H) External Reference No Pipeline Delays Small 12-Pin TQFN Package
Features
MAX1224/MAX1225
Ordering Information
PART MAX1224CTC-T MAX1224ETC-T MAX1225CTC-T MAX1225ETC-T TEMP RANGE 0C to +70C 0C to +70C PINPACKAGE 12 TQFN-12 12 TQFN-12 INPUT Unipolar Unipolar Bipolar Bipolar
-40C to +85C 12 TQFN-12 -40C to +85C 12 TQFN-12
Applications
Data Acquisition Bill Validation Motor Control Communications Portable Instruments
Pin Configuration
TOP VIEW
AIN+ 12 N.C. 11 SCLK 10
10F +2.7V TO +3.6V
Typical Operating Circuit
+1.8V TO VDD
0.01F VDD
0.01F VL DOUT
10F
AINREF RGND
1 2 3
9 8 7
CNVST DOUT VL
DIFFERENTIAL + INPUT VOLTAGE -
AIN+ AIN-
MAX1224 MAX1225
MAX1224 MAX1225
REF 4.7F 0.01F REF RGND
C/DSP CNVST SCLK
4 VDD
5 N.C.
6 GND
GND
TQFN SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V VL to GND ................-0.3V to the lower of (VDD + 0.3V) and +6V Digital Inputs to GND .................-0.3V to the lower of (VDD + 0.3V) and +6V Digital Output to GND ....................-0.3V to the lower of (VL + 0.3V) and +6V Analog Inputs and REF to GND..........-0.3V to the lower of (VDD + 0.3V) and +6V RGND to GND .......................................................-0.3V to +0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 12-Pin TQFN (derate 16.9mW/C above +70C) ......1349mW Operating Temperature Ranges MAX127_ CTC ...................................................0C to +70C MAX127_ ETC.................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL = VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3V and TA = +25C.)
PARAMETER DC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain Temperature Coefficient DYNAMIC SPECIFICATIONS (fIN = 525kHz sine wave, VIN = VREF, unless otherwise noted.) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Minimum Conversion Time Maximum Throughput Rate Minimum Throughput Rate Track-and-Hold Acquisition Time Aperture Delay Aperture Jitter External Clock Frequency fSCLK (Note 6) (Note 7) tACQ (Note 4) (Note 5) tCONV (Note 3) 1.5 10 125 5 30 24.0 0.667 s Msps ksps ns ns ps MHz SINAD THD SFDR IMD fIN1 = 250kHz, fIN2 = 300kHz -3dB point S/(N + D) > 68dB, single ended Up to the 5th harmonic 66 69 -80 -83 -78 15 1.2 -76 -76 dB dB dB dB MHz MHz Offset nulled 2 1 6.0 INL DNL (Note 1) Guaranteed no missing codes (Note 2) 12 -1.5 -1.0 +1.5 +1.5 8.0 Bits LSB LSB LSB ppm/C LSB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V, VL = VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3V and TA = +25C.)
PARAMETER ANALOG INPUTS (AIN+, AIN-) Differential Input Voltage Range Absolute Input Voltage Range DC Leakage Current Input Capacitance Input Current (Average) REFERENCE INPUT (REF) REF Input Voltage Range Input Capacitance DC Leakage Current Input Current (Average) DIGITAL INPUTS (SCLK, CNVST) Input-Voltage Low Input-Voltage High Input Leakage Current DIGITAL OUTPUT (DOUT) Output Load Capacitance Output-Voltage Low Output-Voltage High Output Leakage Current POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage Analog Supply Current, Normal Mode Analog Supply Current, Partial Power-Down Mode Analog Supply Current, Full Power-Down Mode VDD VL Static, fSCLK = 24.0MHz IDD Static, no SCLK Operational, 1.5Msps IDD IDD fSCLK = 24.0MHz No SCLK fSCLK = 24.0MHz No SCLK Operational, full-scale input at 1.5Msps Static, fSCLK = 24.0MHz Digital Supply Current (Note 8) Partial/full power-down mode, fSCLK = 24.0MHz Static, no SCLK, all modes Positive-Supply Rejection PSR Full-scale input, 3V +20%, -10% 2.7 1.8 5 4 6 1 1 1 0.3 0.3 0.15 0.1 0.1 0.2 1 1 0.5 0.3 1 3.0 A mV mA 3.6 VDD 7 5 8 mA A mA V V COUT VOL VOH IOL For stated timing performance ISINK = 5mA, VL 1.8V ISOURCE = 1mA, VL 1.8V Output high impedance VL - 0.5V 0.2 10 30 0.4 pF V V A VIL VIH IIL 0.7 x VL 0.05 10 0.3 x VL V V A Time averaged at maximum throughput rate 200 VREF 1.0 20 1 VDD + 50mV V pF A A Per input pin Time averaged at maximum throughput rate 16 50 VIN AIN+ - AIN-, MAX1224 AIN+ - AIN-, MAX1225 0 -VREF / 2 0 VREF +VREF / 2 VDD 1 V V A pF A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1224/MAX1225
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3
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.6V, VL = VDD, VREF = 2.048V, fSCLK = 24.0MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3V and TA = +25C.)
PARAMETER SCLK Pulse-Width High SYMBOL tCH CONDITIONS VL = 2.7V to VDD VL = 1.8V to VDD, minimum recommended (Note 7) VL = 2.7V to VDD SCLK Pulse-Width Low tCL VL = 1.8V to VDD, minimum recommended (Note 7) CL = 30pF, VL = 2.7V to VDD CL = 30pF, VL = 1.8V to VDD VL = 1.8V to VDD VL = 1.8V to VDD VL = 1.8V to VDD 4 10 20 2 16 18.7 22.5 17 24 ns MIN 18.7 22.5 ns TYP MAX UNITS
SCLK Rise to DOUT Transition DOUT Remains Valid After SCLK CNVST Fall to SCLK Fall CNVST Pulse Width Power-Up Time; Full Power-Down Restart Time; Partial Power-Down
tDOUT tDHOLD tSETUP tCSW tPWR-UP tRCV
ns ns ns ns ms Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset error have been nulled. Note 2: No missing codes over temperature. Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period. Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz. Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th rising edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions. Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance. Note 7: 1.5Msps operation guaranteed for VL > 2.7V. See the Typical Operating Characteristics section for recommended sampling speeds for VL < 2.7V. Note 8: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
VL
CNVST tCSW tSETUP SCLK tCL tCH
DOUT DOUT
6k
DOUT
tDHOLD tDOUT
6k GND a) HIGH-Z TO VOH, VOL TO VOH, AND VOH TO HIGH-Z
CL
CL GND b) HIGH-Z TO VOL, VOH TO VOL, AND VOL TO HIGH-Z
Figure 1. Detailed Serial-Interface Timing
Figure 2. Load Circuits for Enable/Disable Times
4
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1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs
Typical Operating Characteristics
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured at TA = +25C)
MAXIMUM RECOMMENDED fSCLK vs. VL
MAX1224/25 toc01
MAX1224/MAX1225
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (MAX1224)
MAX1224/25 toc02
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (MAX1225)
0.75 0.50 INL (LSB) 0.25 0 -0.25 -0.50 -0.75
MAX1224/25 toc03
25
1.00 0.75 0.50 INL (LSB) 0.25 0 -0.25
1.00
23 fSCLK (MHz)
21
19
-0.50 -0.75
17 1.8 2.1 2.4 2.7 VL (V) 3.0 3.3 3.6
-1.00 0 1024 2048 3072 4096 DIGITAL OUTPUT CODE
-1.00 -2048
-1024
0
1024
2048
DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE (MAX1224)
MAX1224/25 toc04
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE (MAX1225)
MAX1224/25 toc05
OFFSET ERROR vs. TEMPERATURE (MAX1224)
MAX1224/25 toc06
1.00 0.75 0.50 DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 0 1024 2048 3072
1.00 0.75 0.50 DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 -2048
0
OFFSET ERROR (LSB) -1024 0 1024 2048
-1
-2
-3
-4 -40 -15 10 35 60 85 DIGITAL OUTPUT CODE TEMPERATURE (C)
4096
DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE (MAX1225)
MAX1224/25 toc07
GAIN ERROR vs. TEMPERATURE (MAX1224)
MAX1224/25 toc08
GAIN ERROR vs. TEMPERATURE (MAX1225)
MAX1224/25 toc09
2
2
2
OFFSET ERROR (LSB)
1
1 GAIN ERROR (LSB)
1 GAIN ERROR (LSB)
0
0
0
-1
-1
-1
-2 -40 -15 10 35 60 85 TEMPERATURE (C)
-2 -40 -15 10 35 60 85 TEMPERATURE (C)
-2 -40 -15 10 35 60 85 TEMPERATURE (C)
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5
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured at TA = +25C)
DYNAMIC PERFORMANCE vs. INPUT FREQUENCY (MAX1224)
MAX1224/25 toc10
DYNAMIC PERFORMANCE vs. INPUT FREQUENCY (MAX1225)
MAX1224/25 toc11
70.00
69.50
DYNAMIC PERFORMANCE (dB)
DYNAMIC PERFORMANCE (dB)
69.75 SNR 69.50
69.25
SNR
69.00 SINAD 68.75
69.25 SINAD 69.00 100 200 300 400 500 ANALOG INPUT FREQUENCY (kHz)
68.50 100 200 300 400 500 ANALOG INPUT FREQUENCY (kHz)
THD vs. INPUT FREQUENCY
MAX1224 -84
MAX1224/25 toc12
SFDR vs. INPUT FREQUENCY
MAX1224/25 toc13
-82
92
90
SFDR (dB)
THD (dB)
-86
88
MAX1225
-88 MAX1225 -90
86
84 MAX1224
-92 100 200 300 400 500 ANALOG INPUT FREQUENCY (kHz)
82 100 200 300 400 500 ANALOG INPUT FREQUENCY (kHz)
FFT PLOT (MAX1224)
MAX1224/25 toc14
FFT PLOT (MAX1225)
fIN = 500kHz SINAD = 69.2dB SNR = 69.3dB THD = -90.5dB SFDR = 88.15dB
MAX1224/25 toc15
0 -20 -40 -60 -80 -100 -120 -140 0
AMPLITUDE (dB)
AMPLITUDE (dB) 750
fIN = 500kHz SINAD = 69.4dB SNR = 69.6dB THD = -83.9dB SFDR = 84.3dB
0 -20 -40 -60 -80 -100 -120 -140
125
250
375
500
625
0
125
250
375
500
625
750
ANALOG INPUT FREQUENCY (kHz)
ANALOG INPUT FREQUENCY (kHz)
6
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1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured at TA = +25C)
TOTAL HARMONIC DISTORTION vs. SOURCE IMPEDANCE
MAX1224/25 toc16
MAX1224/MAX1225
TWO-TONE IMD PLOT (MAX1224)
fIN1 = 250.102kHz fIN2 = 299.966kHz IMD = -88.4dB fIN1 -60 -80 -100 -120 -140 fIN2
MAX1224/25 toc17 MAX1224/25 toc21 MAX1224/25 toc19
-50
0 -20 -40
-60 fIN = 500kHz THD (dB) -70
-80 fIN = 100kHz -90
-100 10 100 SOURCE IMPEDANCE () 1000
AMPLITUDE (dB)
0
125
250
375
500
625
750
ANALOG INPUT FREQUENCY (kHz)
TWO-TONE IMD PLOT (MAX1225)
MAX1224/25 toc18
0 -20 -40 fIN1 -60 -80 -100 -120 -140 0 125 250 375 500 625 fIN2 fIN1 = 250.102kHz fIN2 = 299.966kHz IMD = -85.2dB
VDD/VL FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE
1.0 VDD/VL SUPPLY CURRENT (A)
0.8
AMPLITUDE (dB)
0.6
VDD, fSCLK = 24MHz
0.4
0.2
VL, NO SCLK
VDD, NO SCLK
750
0 -40 -15 10 35 60 85 TEMPERATURE (C)
ANALOG INPUT FREQUENCY (kHz)
VL PARTIAL/FULL POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE
MAX1224/25 toc20
VDD SUPPLY CURRENT vs. TEMPERATURE
9
100
75 VL = 3V, fSCLK = 24MHz 50 VL = 1.8V, fSCLK = 24MHz 25
VDD SUPPLY CURRENT (mA)
VL SUPPLY CURRENT (A)
CONVERSION 6
3 PARTIAL POWER-DOWN
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
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7
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
Typical Operating Characteristics (continued)
(VDD = +3V, VL = VDD, VREF = 2.048V, fSCLK = 24MHz, fSAMPLE = 1.5Msps, TA = TMIN to TMAX, unless otherwise noted. Typical values are measured at TA = +25C)
VDD SUPPLY CURRENT vs. CONVERSION RATE
MAX1224/25 toc22
VL SUPPLY CURRENT vs. TEMPERATURE
MAX1224/25 toc23
VL SUPPLY CURRENT vs. CONVERSION RATE
MAX1224/25 toc24
9
0.5
250
VDD SUPPLY CURRENT (mA)
VL SUPPLY CURRENT (mA)
6
CONVERSION, VL = 3V 0.3 CONVERSION, VL = 1.8V
VL SUPPLY CURRENT (A)
0.4
200
150
VL = 3V
0.2
100
3
0.1
50 VL = 1.8V
0 0 250 500 750 1000 1250 1500 fSAMPLE (kHz)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 250 500 750 100 1250 1500 fSAMPLE (kHz)
Pin Description
PIN 1 2 3 4 5, 11 6 7 8 9 10 12 -- NAME AINREF RGND VDD N.C. GND VL DOUT CNVST SCLK AIN+ EP Negative Analog Input External Reference Voltage Input. VREF sets the analog input range. Bypass REF with a 0.01F capacitor and a 4.7F capacitor to RGND. Reference Ground. Connect RGND to GND. Positive Analog Supply Voltage (+2.7V to +3.6V). Bypass VDD with a 0.01F capacitor and a 10F capacitor to GND. No Connection Ground. GND is internally connected to EP. Positive Logic Supply Voltage (1.8V to VDD). Bypass VL with a 0.01F capacitor and a 10F capacitor to GND. Serial Data Output. Data is clocked out on the rising edge of SCLK. Convert Start. Forcing CNVST high prepares the part for a conversion. Conversion begins on the falling edge of CNVST. The sampling instant is defined by the falling edge of CNVST. Serial Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion speed. Positive Analog Input Exposed Paddle. EP is internally connected to GND. FUNCTION
8
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1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
VDD VL
AIN+ CIN+ RIN+ CAPACITIVE DAC
REF AIN+ T/H AIN12-BIT SAR ADC OUTPUT BUFFER DOUT
AINCINRINACQUISITION MODE VAZ COMP CONTROL LOGIC
CONTROL LOGIC AND TIMING
CNVST SCLK
AIN+
CIN+
RIN+
CAPACITIVE DAC
MAX1224 MAX1225
RGND GND
AINCINRIN-
VAZ
COMP
CONTROL LOGIC
HOLD/CONVERSION MODE
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit
Detailed Description
The MAX1224/MAX1225 use an input T/H and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 12-bit output. The serial interface requires only three digital lines (SCLK, CNVST, and DOUT) and provides easy interfacing to microprocessors (Ps) and DSPs. Figure 3 shows the simplified internal structure for the MAX1224/MAX1225.
the signal to be acquired. It is calculated by the following equation: tACQ 9 x (RS + RIN) x 16pF where RIN = 200, and RS is the source impedance of the input signal. Note: tACQ is never less than 125ns, and any source impedance below 12 does not significantly affect the ADC's AC performance.
True-Differential Analog Input T/H
The equivalent circuit of Figure 4 shows the input architecture of the MAX1224/MAX1225, which is composed of a T/H, a comparator, and a switched-capacitor digital-to-analog converter (DAC). The T/H enters its tracking mode on the 14th SCLK rising edge of the previous conversion. Upon power-up, the T/H enters its tracking mode immediately. The positive input capacitor is connected to AIN+. The negative input capacitor is connected to AIN-. The T/H enters its hold mode on the falling edge of CNVST and the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens. The acquisition time, tACQ, is the minimum time needed for
Input Bandwidth
The ADC's input-tracking circuitry has a 15MHz smallsignal bandwidth, making it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes that clamp the analog input to VDD and GND allow the analog input pins to swing from GND - 0.3V to VDD + 0.3V without damage. Both inputs must not exceed VDD or be lower than GND for accurate conversions.
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9
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
Serial Interface
Initialization After Power-Up and Starting a Conversion
Upon initial power-up, the MAX1224/MAX1225 require a complete conversion cycle to initialize the internal calibration. Following this initial conversion, the part is ready for normal operation. This initialization is only required after a hardware power-up sequence and is not required after exiting partial or full power-down mode. To start a conversion, pull CNVST low. At CNVST's falling edge, the T/H enters its hold mode and a conversion is initiated. SCLK runs the conversion and the data can then be shifted out serially on DOUT. A CNVST falling edge initiates a conversion sequence: the T/H stage holds the input voltage, the ADC begins to convert, and DOUT changes from high impedance to logic low. SCLK is used to drive the conversion process, and it shifts data out as each bit of the conversion is determined. SCLK begins shifting out the data after the 4th rising edge of SCLK. DOUT transitions t DOUT after each SCLK's rising edge and remains valid 4ns (tDHOLD) after the next rising edge. The 4th rising clock edge produces the MSB of the conversion at DOUT, and the MSB remains valid 4ns after the 5th rising edge. Since there are 12 data bits and 3 leading zeros, at least 16 rising clock edges are needed to shift out these bits. For continuous operation, pull CNVST high between the 14th and the 16th SCLK rising edges. If CNVST stays low after the falling edge of the 16th SCLK cycle, the DOUT line goes to a high-impedance state on either CNVST's rising edge or the next SCLK's rising edge.
Timing and Control
Conversion-start and data-read operations are controlled by the CNVST and SCLK digital inputs. Figures 1 and 5 show timing diagrams, which outline the serialinterface operation.
CNVST tSETUP POWER-MODE SELECTION WINDOW tACQUIRE CONTINUOUS-CONVERSION SELECTION WINDOW 16
SCLK
1
2
3
4
8
14
HIGH IMPEDANCE DOUT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Interface-Timing Sequence
CNVST ONE 8-BIT TRANSFER SCLK 1ST SCLK RISING EDGE DOUT MODE 0 0 0 D11 D10 D9 D8 D7
CONVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
NORMAL
PPD
Figure 6. SPI Interface--Partial Power-Down Mode
10
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1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs
Partial Power-Down and Full Power-Down Modes
Power consumption can be reduced significantly by placing the MAX1224/MAX1225 in either partial power-down mode or full power-down mode. Partial power-down mode is ideal for infrequent data sampling and fast wakeup time applications. Pull CNVST high after the 3rd SCLK rising edge and before the 14th SCLK rising edge to enter and stay in partial power-down mode (see Figure 6). This reduces the supply current to 1mA. Drive CNVST low and allow at least 14 SCLK cycles to elapse before driving CNVST high to exit partial power-down mode. Full power-down mode is ideal for infrequent data sampling and very low supply-current applications. The MAX1224/MAX1225 have to be in partial power-down mode in order to enter full power-down mode. Perform the SCLK/CNVST sequence described above to enter partial power-down mode. Then repeat the same sequence to enter full power-down mode (see Figure 7). Drive CNVST low, and allow at least 14 SCLK cycles to elapse before driving CNVST high to exit full powerdown mode. In partial/full power-down mode, maintain a logic low or a logic high on SCLK to minimize power consumption.
Applications Information
External Reference
An external reference is required for the MAX1224/ MAX1225. Use a 4.7F and 0.01F bypass capacitor on the REF pin for best performance. The reference input structure allows a voltage range of +1V to VDD.
MAX1224/MAX1225
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST and clocked by SCLK, and the resulting data is clocked out on DOUT by SCLK. With SCLK idling high or low, a falling edge on CNVST begins a conversion. This causes the analog input stage to transition from track to hold mode, and for DOUT to transition from high impedance to being actively driven low. A total of 16 SCLK cycles are required to complete a normal conversion. If CNVST is low during the 16th falling SCLK edge, DOUT returns to high impedance on the next rising edge of CNVST or SCLK, enabling the serial interface to be shared by multiple devices. If CNVST returns high after the 14th, but before the 16th SCLK rising edge, DOUT remains active so continuous conversions can be sustained. The highest throughput is achieved when performing continuous conversions. Figure 10 illustrates a conversion using a typical serial interface.
Transfer Function
Figure 8 shows the unipolar transfer function for the MAX1224. Figure 9 shows the bipolar transfer function for the MAX1225. The MAX1224 output is straight binary, while the MAX1225 output is two's complement.
CNVST FIRST 8-BIT TRANSFER SCLK 1ST SCLK RISING EDGE DOUT 0 0 0 D11 D10 D9 1ST SCLK RISING EDGE D8 D7 PPD 0
EXECUTE PARTIAL POWER-DOWN TWICE SECOND 8-BIT TRANSFER
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
0
0
0
0
0
0
0 FPD
MODE
NORMAL
RECOVERY
Figure 7. SPI Interface--Full Power-Down Mode
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11
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
OUTPUT CODE FULL-SCALE TRANSITION
Connection to Standard Interfaces
The MAX1224/MAX1225 serial interface is fully compatible with SPI/QSPI and MICROWIRE (see Figure 11). If a serial interface is available, set the CPU's serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 28.8MHz.
111...111 111...110 111...101
SPI and MICROWIRE
FS = VREF ZS = 0 V 1 LSB = REF 4096 000...011 000...010 000...001 000...000 0 1 2 3 DIFFERENTIAL INPUT VOLTAGE (LSB) FS - 3/2 LSB FS
Figure 8. Unipolar Transfer Function (MAX1224 Only)
When using SPI or MICROWIRE, the MAX1224/MAX1225 are compatible with all four modes programmed with the CPHA and CPOL bits in the SPI or MICROWIRE control register. Conversion begins with a CNVST falling edge. DOUT goes low, indicating a conversion is in progress. Two consecutive 1-byte reads are required to get the full 12 bits from the ADC. DOUT transitions on SCLK rising edges. DOUT is guaranteed to be valid tDOUT later and remains valid until tDHOLD after the following SCLK rising edge. When using CPOL = 0 and CPHA = 0, or CPOL = 1 and CPHA = 1, the data is clocked into the P on the following rising edge. When using CPOL = 0 and CPHA = 1, or CPOL = 1 and CPHA = 0, the data is clocked into the P on the next falling edge. See Figure 11 for connections and Figures 12 and 13 for timing. See the Timing Characteristics section to determine the best mode to use.
QSPI
OUTPUT CODE V FS = REF 2 ZS = 0 -V - FS = REF 2 VREF 1 LSB = 4096 FULL-SCALE TRANSITION
011...111 011...110
000...010 000...001 000...000 111...111 111...110 111...101
Unlike SPI, which requires two 1-byte reads to acquire the 12 bits of data from the ADC, QSPI allows the minimum number of clock cycles necessary to clock in the data. The MAX1224/MAX1225 require 16 clock cycles from the P to clock out the 12 bits of data. Figure 14 shows a transfer using CPOL = 1 and CPHA = 1. The conversion result contains three zeros, followed by the 12 data bits, and a trailing zero with the data in MSBfirst format.
DSP Interface to the TMS320C54_
The MAX1224/MAX1225 can be directly connected to the TMS320C54_ family of DSPs from Texas Instruments, Inc. Set the DSP to generate its own clocks or use external clock signals. Use either the standard or buffered serial port. Figure 15 shows the simplest interface between the MAX1224/MAX1225 and the TMS320C54_, where the transmit serial clock (CLKX) drives the receive serial clock (CLKR) and SCLK, and the transmit frame sync (FSX) drives the receive frame sync (FSR) and CNVST. For continuous conversion, set the serial port to transmit a clock, and pulse the frame sync signal for a clock period before data transmission. The serial-port configuration (SPC) register should be set up with internal
100...001 100...000
-FS
0 DIFFERENTIAL INPUT VOLTAGE (LSB)
FS FS - 3/2 LSB
Figure 9. Bipolar Transfer Function (MAX1225 Only)
12
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1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
CNVST
SCLK
1
14
16
1
DOUT 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
Figure 10. Continuous Conversion with Burst/Continuous Clock
I/O SCK MISO
+3V TO +5V
CNVST SCLK DOUT
MAX1224 MAX1225
SS A) SPI
CS SCK MISO
+3V TO +5V
CNVST SCLK DOUT
MAX1224 MAX1225
SS B) QSPI
I/O SK SI
CNVST SCLK DOUT
MAX1224 MAX1225
C) MICROWIRE
Figure 11. Common Serial-Interface Connections to the MAX1224/MAX1225
______________________________________________________________________________________
13
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
CNVST
1 SCLK HIGH-Z
8
9
16
DOUT
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
Figure 12. SPI/MICROWIRE Serial-Interface Timing--Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
1
14
16
1
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing--Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK HIGH-Z
2
16
HIGH-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
Figure 14. QSPI Serial-Interface Timing--Single Conversion (CPOL = 1, CPHA = 1)
frame sync (TXM = 1), CLKX driven by an on-chip clock source (MCM = 1), burst mode (FSM = 1), and 16-bit word length (FO = 0). This setup allows continuous conversions provided that the data-transmit register (DXR) and the data-receive register (DRR) are serviced before the next conversion. Alternatively, autobuffering can be enabled when using the buffered serial port to execute conversions and read the data without CPU intervention. Connect the VL pin to the TMS320C54_ supply voltage when the MAX1224/MAX1225 are operating with an analog supply voltage higher than the DSP supply voltage. The
word length can be set to 8 bits with FO = 1 to implement the power-down modes. The CNVST pin must idle high to remain in either power-down state. Another method of connecting the MAX1224/MAX1225 to the TMS320C54_ is to generate the clock signals external to either device. This connection is shown in Figure 16, where serial clock (CLOCK) drives the CLKR, and SCLK and the convert signal (CONVERT) drive the FSR and CNVST. The serial port must be set up to accept an external receive-clock and external receive-frame sync.
14
______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs
The SPC register should be written as follows: TXM = 0, external frame sync MCM = 0, CLKX is taken from the CLKX pin FSM = 1, burst mode FO = 0, data transmitted/received as 16-bit words This setup allows continuous conversion, provided that the DRR is serviced before the next conversion. Alternatively, autobuffering can be enabled when using the buffered serial port to read the data without CPU intervention. Connect the VL pin to the TMS320C54_ supply voltage when the MAX1224/MAX1225 are operating with an analog supply voltage higher than the DSP supply voltage. The MAX1224/MAX1225 can also be connected to the TMS320C54_ by using the data transmit (DX) pin to drive CNVST and the CLKX generated internally to drive SCLK. A pullup resistor is required on the CNVST signal to keep it high when DX goes high impedance and 0001hex should be written to the DXR continuously for continuous conversions. The power-down modes may be entered by writing 00FFhex to the DXR (see Figures 17 and 18).
MAX1224/MAX1225
VL
DVDD CLKX TMS320C54_ CLKR FSX FSR
DSP Interface to the ADSP21_ _ _
The MAX1224/MAX1225 can be directly connected to the ADSP21_ _ _ family of DSPs from Analog Devices, Inc. Figure 19 shows the direct connection of the MAX1224/MAX1225 to the ADSP21_ _ _. There are two modes of operation that can be programmed to interface with the MAX1224/MAX1225. For continuous conversions, idle CNVST low and pulse it high for one clock cycle during the LSB of the previous transmitted word. The ADSP21_ _ _ STCTL and SRCTL registers should be configured for early framing (LAFR = 0) and for an active-high frame (LTFS = 0, LRFS = 0) signal. In this mode, the data-independent frame-sync bit (DITFS = 1) can be selected to eliminate the need for writing to the transmit-data register more than once. For single conversions, idle CNVST high and pulse it low for the entire conversion. The ADSP21_ _ _ STCTL and SRCTL registers should be configured for late framing (LAFR = 1) and for an active-low frame (LTFS = 1, LRFS = 1) signal. This is also the best way to enter the power-down modes by setting the word length to 8 bits (SLEN = 1001). Connect the VL pin to the ADSP21_ _ _ supply voltage when the MAX1224/MAX1225 are operating with a supply voltage higher than the DSP supply voltage (see Figures 17 and 18).
MAX1224 SCLK MAX1225
CNVST
DOUT
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
VL
DVDD
MAX1224 MAX1225 SCLK
CNVST DOUT
TMS320C54_
CLKR FSR DR
CLOCK CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
CNVST
SCLK
1
1
DOUT
D0
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
Figure 17. DSP Interface--Continuous Conversion ______________________________________________________________________________________ 15
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
CNVST
SCLK
1
1
DOUT
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 18. DSP Interface--Single-Conversion, Continuous/Burst Clock
VL
VDDINT TCLK RCLK TFS RFS
MAX1224 SCLK MAX1225
CNVST
ADSP21_ _ _
DOUT
DR
Figure 19. Interfacing to the ADSP21_ _ _
Figure 20 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at GND, separate from the logic ground. Connect all other analog grounds and DGND to this star ground point for further noise reduction. The ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the V DD power supply can affect the ADC's high-speed comparator. Bypass this supply to the single-point analog ground with 0.01F and 10F bypass capacitors. Minimize capacitor lead lengths for best supply-noise rejection.
Definitions
SUPPLIES GND VL
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1224/MAX1225 are measured using the end-points method.
10F 10F 0.1F
0.1F
Differential Nonlinearity
GND RGND VL DGND DIGITAL CIRCUITRY VL
VDD
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of 1 LSB or less guarantees no missing codes and a monotonic transfer function.
MAX1224 MAX1225 Figure 20. Power-Supply Grounding Condition
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Aperture Delay Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package.
16
Aperture delay (tAD) is the time defined between the falling edge of CNVST and the instant when an actual sample is taken.
______________________________________________________________________________________
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The theoretical minimum analog-todigital noise is caused by quantization error, and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. where V 1 is the fundamental amplitude, and V 2 through V5 are the amplitudes of the 2nd- through 5thorder harmonics.
MAX1224/MAX1225
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component.
Full-Power Bandwidth
Full-power bandwidth is the frequency at which the input signal amplitude attenuates by 3dB for a full-scale input.
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signal-to-noise plus distortion (SINAD) is equal to 68dB.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Intermodulation Distortion (IMD)
Any device with nonlinearities creates distortion products when two sine waves at two different frequencies (f1 and f2) are input into the device. Intermodulation distortion (IMD) is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones, f1 and f2. The individual input tone levels are at -7dBFS. The intermodulation products are as follows: * 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1 * 3rd-order intermodulation products (IM3): 2f1 - f2, 2f2 - f1, 2f1 + f2, 2f2 + f1 * 4th-order intermodulation products (IM4): 3f1 - f2, 3f2 - f1, 3f1 + f2, 3f2 + f1 * 5th-order intermodulation products (IM5): 3f1 - 2f2, 3f2 - 2f1, 3f1 + 2f2, 3f2 + 2f1
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows: ENOB = (SINAD - 1.76) 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 x log
2 2 2 2 V2 + V3 + V4 + V5 V1
Chip Information
TRANSISTOR COUNT: 13,016 PROCESS: BiCMOS
______________________________________________________________________________________
17
1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs MAX1224/MAX1225
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
24L QFN THIN.EPS
PACKAGEOUTLINE 12,16,20,24LTHINQFN,4x4x0.8mm
21-0139
C
1
2
PACKAGEOUTLINE 12,16,20,24LTHINQFN,4x4x0.8mm
21-0139
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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